Edgar Reyes-Rivera
Dual Major Computer Engineering & Computer Science Student
I'm passionate about building robust, high-performance systems from the ground up. I thrive on the challenges found at the intersection of hardware and software.
Featured Work
A selection of my recent projects. See all projects here.
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TinyRISC-V RV1 Processor
Completed
A single-cycle 32-bit RISC-V processor (RV1) in Verilog, supporting a subset of the RISC-V ISA.
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FPGA-Based Gaussian Blur Image Processing
Completed
Engineered a Gaussian blur filter on a Cyclone V SOC FPGA using Verilog, processing a 160x120 image through a 3x3 kernel.