My Projects
A collection of my technical projects, from hardware design to full-stack software.
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Trading Strategy Research System
Completed
A Python research system with an anti-lookahead backtest engine and walk-forward validation that tested 3 classical strategies across 25 tickers — and produced a null result rigorous enough to trust.
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CIFAR-10 CNN Design and Ablation Study
Completed
A ten-layer convolutional network for CIFAR-10 designed through twelve controlled experiments, reaching 92.2% test accuracy — nearly 17 points over the course baseline.
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Cell Segmentation with Classical Machine Learning
Completed
A per-pixel segmentation pipeline for fluorescence microscopy that compares four classical classifiers on the Cell Tracking Challenge — and finds that feature engineering, not model complexity, drives accuracy.
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Obstacle-Avoiding Arduino Robot
Completed
An IR-remote-controlled differential-drive robot that holds a straight line with encoder feedback and steers itself around obstacles using a servo-mounted ultrasonic sensor.
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Focus & Habit Dashboard
Completed
A habit, task, and focus-timer dashboard in a single static HTML file — offline-first, syncing across devices through Firebase, with no build step at all.
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Personal Portfolio Website
In-Progress
This website — a fully static portfolio built with Astro, with type-safe content collections, a token-based design system, and automated deployment on Cloudflare.
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TinyRV1 RISC-V Processor
Completed
A single-cycle 32-bit RISC-V processor in Verilog on a DE1-SoC FPGA, with push-button single-stepping, live register inspection on the 7-segment displays, and a custom Python assembler.
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FPGA-Based Gaussian Blur Image Processing
Completed
A hardware Gaussian blur filter in Verilog on a DE1-SoC FPGA — a custom state machine convolves a 160x120 image with a 3x3 kernel and drives a VGA display.
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FPGA Neural Network Inference Accelerator
Future
A 4×4 integer matrix multiply accelerator in SystemVerilog on a Zynq SoC, driven from ARM Linux over AXI4-Lite and demonstrated on a real MNIST network layer.
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Heterogeneous Computing Performance Analysis Suite
Future
One computation implemented four ways — naive CPU, AVX2 SIMD, CUDA, and distributed multi-GPU — with roofline modeling to explain where performance actually comes from.
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FPGA Network Packet Parser
In-Progress
A UDP-style packet parser built as a SystemVerilog state machine on a Zynq SoC, exposing parsed header fields to the ARM cores over AXI4-Lite with a measured hardware-vs-software latency comparison.